Microelectronic package and method of manufacturing same

ABSTRACT

A microelectronic package includes a substrate ( 110 ), a die ( 120 ) embedded within the substrate, the die having a front side ( 121 ) and a back side ( 122 ) and a through-silicon-via ( 123 ) therein, build-up layers ( 130 ) built up over the front side of the die, and a power plane ( 140 ) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate ( 210 ), a first die ( 220 ) and a second die ( 260 ) embedded in the substrate and having a front side ( 221, 261 ) and a back side ( 222, 262 ) and a through-silicon-via ( 223, 263 ) therein, build-up layers ( 230 ) over the front sides of the first and second dies, and an electrically conductive structure ( 240 ) in physical contact with the back sides of the first and second dies.

FIELD OF THE INVENTION

The disclosed embodiments of the invention relate generally tomicroelectronic packages and relate more particularly to bumplessbuild-up layer packages.

BACKGROUND OF THE INVENTION

Bumpless Build-Up Layer (BBUL) is a packaging technology formicroelectronic devices in which the package includes at least one die(also referred to as a “chip”) embedded in a substrate with one or morebuild-up layers formed over the substrate. Electrical connectionsbetween the build-up layers and the die bond pads may be made usingstandard microvia formation processes. BBUL packages enable smallelectrical loop inductance and reduced thermomechanical stresses on lowdielectric constant (low-k) die materials. They also allow high leadcount, ready integration of multiple electronic and optical components(such as logic, memory, radio frequency (RF), and microelectromechanicalsystems (MEMS), among others), and inherent scalability. Existingprocess flows for BBUL packages involve the building of the substrate ona temporary core/carrier capped with a copper foil that is etched offafter the package is separated from the core/carrier.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed embodiments will be better understood from a reading ofthe following detailed description, taken in conjunction with theaccompanying figures in the drawings in which:

FIGS. 1A and 1B are, respectively, a plan view and a cross-sectionalview of a microelectronic package according to an embodiment of theinvention;

FIGS. 2A and 2B are, respectively, a plan view and a cross-sectionalview of a microelectronic package according to another embodiment of theinvention;

FIG. 3 is a cross-sectional view of a multi-chip package according to anembodiment of the invention;

FIG. 4 is a flowchart illustrating a method of manufacturing amicroelectronic package according to an embodiment of the invention;

FIG. 5 is a cross-sectional view of a portion of a microelectronicpackage at a particular point in its manufacturing process according toan embodiment of the invention; and

FIG. 6 is a cross-sectional view of a portion of the microelectronicpackage of FIG. 5 at a subsequent point in its manufacturing processaccording to an embodiment of the invention.

For simplicity and clarity of illustration, the drawing figuresillustrate the general manner of construction, and descriptions anddetails of well-known features and techniques may be omitted to avoidunnecessarily obscuring the discussion of the described embodiments ofthe invention. Additionally, elements in the drawing figures are notnecessarily drawn to scale. For example, the dimensions of some of theelements in the figures may be exaggerated relative to other elements tohelp improve understanding of embodiments of the present invention. Thesame reference numerals in different figures denote the same elements,while similar reference numerals may, but do not necessarily, denotesimilar elements.

The terms “first,” “second,” “third,” “fourth,” and the like in thedescription and in the claims, if any, are used for distinguishingbetween similar elements and not necessarily for describing a particularsequential or chronological order. It is to be understood that the termsso used are interchangeable under appropriate circumstances such thatthe embodiments of the invention described herein are, for example,capable of operation in sequences other than those illustrated orotherwise described herein. Similarly, if a method is described hereinas comprising a series of steps, the order of such steps as presentedherein is not necessarily the only order in which such steps may beperformed, and certain of the stated steps may possibly be omittedand/or certain other steps not described herein may possibly be added tothe method. Furthermore, the terms “comprise,” “include,” “have,” andany variations thereof, are intended to cover a non-exclusive inclusion,such that a process, method, article, or apparatus that comprises a listof elements is not necessarily limited to those elements, but mayinclude other elements not expressly listed or inherent to such process,method, article, or apparatus.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,”“under,” and the like in the description and in the claims, if any, areused for descriptive purposes and not necessarily for describingpermanent relative positions unless otherwise indicated eitherspecifically or by context. It is to be understood that the terms soused are interchangeable under appropriate circumstances such that theembodiments of the invention described herein are, for example, capableof operation in other orientations than those illustrated or otherwisedescribed herein. The term “coupled,” as used herein, is defined asdirectly or indirectly connected in an electrical or non-electricalmanner. Objects described herein as being “adjacent to” each other maybe in physical contact with each other, in close proximity to eachother, or in the same general region or area as each other, asappropriate for the context in which the phrase is used. Occurrences ofthe phrase “in one embodiment” herein do not necessarily all refer tothe same embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

In one embodiment of the invention, a microelectronic package comprisesa substrate, a die (which may also be referred to herein as a chip)embedded within the substrate—the die having a front side and anopposing back side and further having at least one through-silicon-viatherein, a plurality of build-up layers adjacent to and built up overthe front side of the die, and a power plane adjacent to and in physicalcontact with the back side of the die. In another embodiment, themicroelectronic package comprises a substrate, a first die and a seconddie, both of which are embedded in the substrate, both of which have afront side and an opposing back side, and both of which have at leastone through-silicon-via therein, a plurality of build-up layers adjacentto and built up over the front sides of the first and second dies, andan electrically conductive structure adjacent to and in physical contactwith the back sides of the first and second dies.

As the following discussion will make clear, embodiments of theinvention enable a reduction in the number of power bumps (or otherkinds of bumps) on the active side of a die, thus facilitating areduction in die size. Furthermore, embodiments of the invention enablewhat may be referred to as Die-Down Power-Up (DDPU) systems, which amongother advantages offer better second level interconnect (SLI) returnpath optimization, make possible increased signal-to-ground for theinput/output (I/O) elements, and eliminate troublesome tradeoffs betweenI/O and power. The same or other embodiments of the invention enable anincrease in achievable I/O density between multiple dies in the package.

Referring now to the drawings, FIG. 1A is a plan view and FIG. 1B is across-sectional view of a microelectronic package 100 according to anembodiment of the invention. FIG. 1B is taken along a line B-B in FIG.1A. As illustrated in FIGS. 1A and 1B, microelectronic package 100comprises a substrate 110 and a die 120 that is embedded withinsubstrate 110. Die 120 has a front side 121 (i.e., the side on which thetransistors (not shown) are located) and an opposing back side 122. Die120 further has therein a through-silicon-via (TSV) 123 that extends allthe way to and is exposed at back side 122. Substrate 110 comprises aplurality of build-up layers 130 (one of which is a dielectric layer139) adjacent to and built up over (and around) front side 121 of die120.

Microelectronic package 100 further comprises a power plane 140 adjacentto and in physical contact with back side 122 of die 120. A thickness ofpower plane 140 may be dictated by the power delivery requirements ofmicroelectronic package 100. The presence of power plane 140 enables areduction in the number of power bumps (or I/O bumps or possibly dummybumps) on front side 121, as well as a corresponding reduction in thesize of die 120, because some of the required bumps may instead beformed within power plane 140 in a location (back side 122) that wasformerly unused or wasted space. In other words, by moving some power orother bumps to back side 122, embodiments of the invention enable areduction in die footprint without compromising on power and I/Ocapability. Furthermore, embodiments of the invention allow powercircuits to be brought into the die either from the bottom or from thetop of the die (or both), whereas previously all power had to be broughtin from the bottom. (This was true even if power was brought in to thetop side of a package; i.e., top side package power would have to berouted to and brought into the die from the bottom side of the die.)Embodiments of the invention eliminate that requirement, and insteadenable a two-sided, functional part where before the only functionalparts were one-sided.

As mentioned, embodiments of the invention enable DDPU systems, in whichpower is brought into a die from a side opposite that where the activedevices are located. As was also mentioned, DDPU systems, by providingmore bumps (even in a smaller footprint), enjoy advantages such asimproved SLI return path optimization and increased I/O signal to groundratio.

Power plane 140 rests on top of the exposed portion of TSV 123 at backside 122, meaning that a connection may be made between power plane 140and TSV 123 (and from there to other parts of die 120) without the needfor any connection bumps at back side 122. In one embodiment, powerplane 140 comprises copper, a material that is compatible with existingequipment and technology processes. In the illustrated embodiment,microelectronic package 100 further comprises a protective layer 150located over power plane 140 in order to protect the power plane frommechanical or environmental damage (such as oxidation) or the like. (Inorder to permit greater clarity of illustration, protective layer 150 isnot shown in FIG. 1A.) As an example, protective layer 150 can be analuminum oxide or a similar layer formed as a result of a chemicaltreatment performed to reduce corrosion and the like. As anotherexample, protective layer 150 can be an overmold made of a polymermaterial, a fiber-reinforced plastic, or the like.

Although not shown in FIGS. 1A and 1B, power plane 140 may in certainembodiments act as an attachment point for one or more passivecomponents (e.g., capacitors, inductors, etc.). In some of these (orother) non-illustrated embodiments, power plane 140 may have a recesstherein that encloses some or all of die 120. This recessedconfiguration allows the overall thickness (often referred to as theZ-height) of microelectronic package 100 to be reduced such that itwould, among other advantages, be compatible with devices and productshaving smaller form factors.

FIG. 1A depicts a perimeter 124 of die 120. FIG. 1B shows only twoendpoints 125 of perimeter 124 and only shows an outer boundary 126 ofan extension of that perimeter through substrate 110. That extension (orfootprint) defines a die area 127, the lateral extent of which isindicated in FIG. 1B. It may be seen that build-up layers 130 contain aplurality of vias 131 outside die area 127 and a plurality of vias 132inside die area 127. In the illustrated embodiment, vias 131electrically connect power plane 140 and substrate 110 to each other andvias 132 electrically connect die 120 and substrate 110 to each other.

Vias 131 that are outside die area 127 require a larger drill sizebecause they are piercing through a thicker dielectric—in other words,they are longer. In that regard, an additional advantage of the recessedconfiguration described above is that it would reduce the aspect ratioof the POP vias (vias 131) thus making those vias easier and cheaper tomanufacture. Vias 132 are shorter because they just have to reach to die120 and not all the way to carrier 140. Thus, smaller lasers could beused for vias 132 than for vias 131. As an example, the vias can becreated using semi-additive process (SAP) techniques, laser projectionpatterning (LPP) techniques, or any other suitable via formationtechnique.

FIG. 2A is a plan view and FIG. 2B is a cross-sectional view of amicroelectronic package 200 according to an embodiment of the invention.FIG. 2B is taken along a line B-B in FIG. 2A. As illustrated in FIGS. 2Aand 2B, microelectronic package 200 comprises a substrate 210 with a die220 and a die 260 embedded therein. Die 220 has a front side 221 (i.e.,the side on which the transistors (not shown) are located) and anopposing back side 222. Die 220 further has therein a TSV 223 thatextends all the way to and is exposed at back side 222. Similarly, die260 has a front side 261 (again, the side on which the transistors (notshown) are located) and an opposing back side 262. Die 260 further hastherein a TSV 263 that extends all the way to and is exposed at backside 262. Substrate 210 comprises a plurality of build-up layers 230(one of which is a dielectric layer 239) adjacent to and built up over(and around) front sides 221 and 261 of dies 220 and 260.

Microelectronic package 200 further comprises an electrically conductivestructure 240 adjacent to and in physical contact with back side 222 ofdie 220 and back side 262 of die 260. In the illustrated embodiment,electrically conductive structure 240 comprises an interconnect 241(e.g., an I/O inter-die connection) that electrically connects back side222 of die 220 and back side 262 of die 260 to each other. Electricallyconductive structure 240 further comprises die connection pads 242 thatcan be used for die stacking (Die stacking according to embodiments ofthe invention, including the role of die connection pads 242, will befurther discussed below.)

In one embodiment, electrically conductive structure 240 comprisescopper. In the same or another embodiment microelectronic package 200further comprises a protective layer 250 over electrically conductivestructure 240 in order to protect the electrically conductive structurefrom mechanical or environmental damage or the like. (In order to permitgreater clarity of illustration, protective layer 250 is not shown inFIG. 2A.) As an example, protective layer 250 can be similar toprotective layer 150 that is shown in FIGS. 1A and 1B.

In one embodiment, electrically conductive structure 240 may have arecess (not shown) therein that encloses some or all of dies 220 and260. In certain embodiments, electrically conductive structure 240 maycontain separate recesses for each die.

An extension (or footprint) of dies 220 and 260 (including the area inbetween them) defines a die area 227, the lateral extent of which isindicated in FIG. 2B. It may be seen that build-up layers 230 contain aplurality of vias 231 outside die area 227 and a plurality of vias 232inside die area 227. In the illustrated embodiment, plurality of vias231 electrically connect die connection pads 242 and substrate 210 toeach other and plurality of vias 232 electrically connect dies 220 and260 and substrate 210 to each other. As shown, die connection pads 242can be located both on top of vias 232 and on top of TSVs not used forI/O connections.

Die-to-die interconnects in a multi-chip package environment are veryexpensive and difficult to scale down in order to keep up with overalldevice scaling. These difficulties and expenses are reduced or avoidedby embodiments of the invention, which increase interconnect density notby reducing line and space width but by placing some of theinterconnects in a previously-unused location: the back side of thedies. Embodiments of the invention may thus be used to roughly doublethe number of interconnects that a given die size may accommodate.

FIG. 3 is a cross-sectional view of a multi-chip package 300 accordingto an embodiment of the invention that includes microelectronic package200, with its dies 220 and 260, as well as an additional die 310. Die310 is connected to die connection pads 242, and thus to vias 231 andsubstrate 210, by interconnects 311. In a non-illustrated embodiment,wire bonds or other connection mechanisms may be used in place of thesolder connections shown in FIG. 3. This and other package on package(POP) or package in package (PIP) configurations are desirable in thatthey have a greatly reduced height or thickness because of the BBULarchitecture. Moreover, embodiments of the invention enable I/Os to bemuch more dense than is true for existing POP architectures, whereperhaps two or three rows of bumps (on which to land an additionalpackage) are all that the package can accommodate, and all of theconnections on the outside of the overall package have to go through thebottom package before being routed to the die. Embodiments of theinvention allow some or all such connections to be formed on the dieback side and also allow them to be more dense. Entire arrays ofconnections are possible, where even the back sides of the dies are atleast partially covered with connections. Furthermore, the electricallyconductive structure itself can serve as an additional routing layer.

FIG. 4 is a flowchart illustrating a method 400 of manufacturing amicroelectronic package according to an embodiment of the invention. Asan example, method 400 may result in the formation of a microelectronicpackage that is similar to microelectronic package 100 that is shown inFIGS. 1A and 1B or to microelectronic package 200 that is shown in FIGS.2A, 2B, and 3.

A step 410 of method 400 is to provide an electrically conductivecarrier. As an example, the electrically conductive carrier can besimilar to an electrically conductive carrier 510 that is first shown inFIG. 5. This electrically conductive carrier can be, for example, acopper foil or the like attached to a peelable core or other temporaryor sacrificial carrier structure. The thickness of the foil may bedictated by the power delivery requirements of the microelectronicpackage. If desired, a multi-layer foil may be used, possibly with arecess that may (in a subsequent step) receive a die. A multi-layer foilmay provide needed flexibility in cases where the foil thickness abovethe die, for example, needs to be different from the foil thicknesselsewhere. As other examples, a multi-layer foil may also offeradvantages in terms of the creation of multi-layer passive devices, andit may help improve warpage.

A step 420 of method 400 is to provide a die having a front side, anopposing back side, and at least one through-silicon-via therein. As anexample, the die can be similar to one or more of die 120, die 220, anddie 260, shown in FIGS. 1A, 1B, 2A, 2B, and 3, and can also be similarto a die 520 that is first shown in FIG. 5. As illustrated, die 520 hasa front side 521, a back side 522, and a TSV 523. In certainembodiments, multiple dies may be provided, as illustrated by the second(unlabeled) die shown in FIG. 5. (It should be understood that thenumber of dies is not limited to just one or two; rather, any number ofdies, as required or appropriate for the desired microelectronicpackage, may be provided.)

A step 430 of method 400 is to attach the back side of the die to theelectrically conductive carrier. This can be achieved, for example, bydispensing conductive adhesive or solder or the like on the TSV pads(or, if the TSVs do not have pads, on the ends of the TSVs themselves)and using thermo-compression bonding or the like to adhere the die (ordies) onto the foil. As an example, these connections may serve todeliver power to the die. FIG. 5 depicts die 520 after it has alreadybeen attached to back side 522 of die 520.

A step 440 of method 400 is to form a plurality of build-up layers overthe front side of the die. A first (or an early) portion of this stepmay be to laminate or otherwise form a dielectric film on the entirepanel, thus providing a level plane for the balance of the build-upprocess. Roughening of the copper film may be performed prior tolamination in order to aid with adhesion to the dielectric film. Smallervias may be formed in the die area landing on the pads (e.g., copperpads) on the die. Larger vias may be formed outside the die area toconnect the electrically conductive carrier (after it is functionalizedas described below) into the substrate or to connect to pads that can beused to stack additional die or packages on top of the micro electronicpackage.

Additional layers may then be built up over the dielectric film. Forexample, SAP techniques may be used to plate the vias landing on the diepads and the first metal layer of the substrate portion of the package.LPP or other techniques may also be used. I/O connections to and fromthe die can be made on first metal layer or on subsequent layers, whichmay be formed using standard substrate SAP (or other) build-up methodsto form the remainder of the package. When the build-up is complete, thepackage together with the copper foil may be separated off the remainderof the temporary core/carrier.

As an example, the build-up layers, the larger vias, the smaller vias,and the dielectric film can be similar to, respectively, build-up layers630, vias 631, vias 632, and dielectric film 639, all of which are shownin FIG. 6. Build-up layers 630 can also be similar to build-up layers130 (shown in FIG. 1B) and 230 (first shown in FIG. 2B). Vias 631 canalso be similar to vias 131 (see FIG. 1B) and 231 (see FIGS. 2B and 3),while vias 632 can also be similar to vias 132 (see FIG. 1B) and 232(see FIGS. 2B and 3). Dielectric film 639 can also be similar todielectric layers 139 (see FIGS. 1A and 1B) and 239 (see FIGS. 2A, 2B,and 3).

A step 450 of method 400 is to pattern the electrically conductivecarrier in order to form an electrically conductive component of themicroelectronic package. In one embodiment this electrically conductivecomponent is a power plane. FIGS. 1A and 1B show an example of amicroelectronic package that results from the performance of thisembodiment of method 400.

In a particular embodiment, step 450 or another step can compriseelectrically connecting the power plane and the substrate to a powersource (e.g., a power rail). As an example, step 450 may compriselaminating dry film or the like on the top of the copper foil and thenperforming subtractive patterning in order to form the power plane.Connections may be made on this to connect the power from the powercarrying vias outside the die to the die through the TSVs.

In another embodiment (where the microelectronic package comprisesmultiple dies) the electrically conductive component is an electricalconnection between two (or more) of the dies. FIGS. 2A, 2B, and 3 showan example of a microelectronic package that results from theperformance of this embodiment of method 400. As an example, step 450may comprise laminating dry film or the like on the top of the copperfoil and then performing subtractive patterning in order to formadditional I/O connections through the TSVs. Pads that can be used tostack die or packages on top can also be created both on top of viasoutside the die area and on top of the TSVs not used for I/Oconnections. These pads can be similar to die connection pads 242 thatare first shown in FIGS. 2A and 2B.

Although the invention has been described with reference to specificembodiments, it will be understood by those skilled in the art thatvarious changes may be made without departing from the spirit or scopeof the invention. Accordingly, the disclosure of embodiments of theinvention is intended to be illustrative of the scope of the inventionand is not intended to be limiting. It is intended that the scope of theinvention shall be limited only to the extent required by the appendedclaims. For example, to one of ordinary skill in the art, it will bereadily apparent that the microelectronic packages and the relatedstructures and methods discussed herein may be implemented in a varietyof embodiments, and that the foregoing discussion of certain of theseembodiments does not necessarily represent a complete description of allpossible embodiments.

Additionally, benefits, other advantages, and solutions to problems havebeen described with regard to specific embodiments. The benefits,advantages, solutions to problems, and any element or elements that maycause any benefit, advantage, or solution to occur or become morepronounced, however, are not to be construed as critical, required, oressential features or elements of any or all of the claims.

Moreover, embodiments and limitations disclosed herein are not dedicatedto the public under the doctrine of dedication if the embodiments and/orlimitations: (1) are not expressly claimed in the claims; and (2) are orare potentially equivalents of express elements and/or limitations inthe claims under the doctrine of equivalents.

1. A microelectronic package comprising: a substrate; a die embeddedwithin the substrate, the die having a front side and an opposing backside and further having at least one through-silicon-via therein; aplurality of build-up layers adjacent to and built up over the frontside of the die; and a power plane adjacent to and in physical contactwith the back side of the die.
 2. The microelectronic package of claim 1wherein: the power plane comprises copper.
 3. The microelectronicpackage of claim 1 further comprising: a passive component attached tothe power plane.
 4. The microelectronic package of claim 1 furthercomprising: a protective layer over the power plane.
 5. Themicroelectronic package of claim 1 wherein: the power plane has a recesstherein; and the die is at least partially located within the recess. 6.The microelectronic package of claim 1 wherein: the die has a dieperimeter; an extension of the die perimeter through the build-up layersdefines a die area; and the build-up layers contain a first plurality ofvias outside the die area and a second plurality of vias inside the diearea.
 7. The microelectronic package of claim 6 wherein: the firstplurality of vias electrically connect the power plane and the substrateto each other; and the second plurality of vias electrically connect thedie and the substrate to each other.
 8. A microelectronic packagecomprising: a substrate; a first die and a second die, both of which areembedded in the substrate, both of which have a front side and anopposing back side, and both of which have at least onethrough-silicon-via therein; a plurality of build-up layers adjacent toand built up over the front sides of the first and second dies; and anelectrically conductive structure adjacent to and in physical contactwith the back sides of the first and second dies.
 9. The microelectronicpackage of claim 8 wherein: the electrically conductive structurecomprises: an interconnect that electrically connects the back sides ofthe first and second dies to each other; and a die connection pad. 10.The microelectronic package of claim 9 wherein: the first die has afirst die perimeter and the second die has a second die perimeter; anextension of the first and second die perimeters through the build-uplayers defines a die area; and the build-up layers contain a firstplurality of vias outside the die area and a second plurality of viasinside the die area.
 11. The microelectronic package of claim 10wherein: the first plurality of vias electrically connect the dieconnection pad and the substrate to each other; and the second pluralityof vias electrically connect the first and second dies and the substrateto each other.
 12. The microelectronic package of claim 8 wherein: theelectrically conductive structure comprises copper.
 13. Themicroelectronic package of claim 8 further comprising: a protectivelayer over the electrically conductive structure.
 14. Themicroelectronic package of claim 8 wherein: the electrically conductivestructure has a recess therein; and the first die and the second die areat least partially located within the recess.
 15. A method ofmanufacturing a microelectronic package, the method comprising:providing an electrically conductive carrier; providing a die having afront side, an opposing back side, and at least one through-silicon-viatherein; attaching the back side of the die to the electricallyconductive carrier; forming a plurality of build-up layers over thefront side of the die, the build-up layers and the electricallyconductive carrier forming part of a substrate of the microelectronicpackage; and patterning the electrically conductive carrier in order toform an electrically conductive component of the microelectronicpackage.
 16. The method of claim 15 wherein: the electrically conductivecomponent is a power plane.
 17. The method of claim 16 furthercomprising: electrically connecting the power plane to a power source;and electrically connecting the substrate to the power source.
 18. Themethod of claim 15 wherein: the microelectronic package furthercomprises a second die; and the electrically conductive component is anelectrical connection between the die and the second die.
 19. The methodof claim 15 wherein: the electrically conductive carrier comprisescopper.
 20. The method of claim 15 further comprising: forming aplurality of connection pads adjacent to the electrically conductivecomponent.
 21. The method of claim 15 wherein: providing theelectrically conductive carrier comprises providing a copper foilattached to a sacrificial core; the method further comprises separatingthe copper foil from the sacrificial core after the build-up layers arecompleted; and patterning the electrically conductive carrier in orderto form the electrically conductive component of the microelectronicpackage comprises patterning the copper foil.